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Hardware Schematic Diagram
The voltage and contrast settings must be configured before the LCD panel is ready for
operation. Figure C-6 shows the initialization procedure required to set up the LCD
controller.
S et u p In s tr u ction Flow
Power ON
Bo a rd Power Su pply S t a rt
RE S ETB Pin i s Kept LOW
S t a rt FPGA Config u r a tion
RE S ETB Pin i s Kept LOW
FPGA Config u red a nd Applic a tion R u nning
RE S ETB Pin i s T a ken HIGH
ADC S elect
- ADC = 0 S EG1 --> S EG132
- ADC = 1 S EG132 --> S EG1
S HL S elect
- S HL = 0 COM1 --> COM64
- S HL = 1 COM64 --> COM1
ADC S elect
S HL S elect
LCD Bi as S elect
Volt a ge Converter ON
Volt a ge Reg u l a tor ON
Volt a ge Follower ON
Reg u l a tor Re s i s tor S elect
S et Reference Volt a ge
End Initi a liz a tion
LCD Bi as
DUTY0, 1 i s "11".
LCD Bi as 0 = 1/7
LCD Bi as 1 = 1/9
W a it longer th a n 1 m s b etween
e a ch in s tr u ction to let the volt a ge s s t ab ilize.
The on-chip re s i s tor s a re us ed.
Therefore, the s election MU S T b e
s et to 101.
S etting Reference Volt a ge
i s a two-p ass in s tr u ction:
- S et Reference Volt a ge Mode
- S et Reference Volt a ge Regi s ter
UG199_C_06_050106
Figure C-6:
LCD Controller Initialization Flow
Operation Example of the 6412 8 EFCBC- 3 LP
The KS0713 LCD controller has several default settings of operation on the LCD panel
PCB. Some settings are forced through direct bonding on the chip. The default settings are:
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Master mode
Parallel mode
Internal oscillator
Duty cycle ratio is set to 1/65
Voltage converter input is between 2.4V ≤ VDD ≤ 3.6V, where VDD connects to 3.3V
Internal voltage divider resistors
Temperature coefficient is set to -0.05%/ ° C
Normal power mode is set
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
www.xilinx.com
127
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